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? semiconductor components industries, llc, 2015 august, 2015 ? rev. 7 1 publication order number: ncv8852/d ncv8852 automotive grade non-synchronous buck controller the ncv8852 is an adjustable?output non?synchronous buck controller which drives an external p?channel mosfet. the device uses peak current mode control with internal slope compensation. the ic incorporates an internal regulator that supplies charge to the gate driver. protection features include internal soft?start, undervoltage lockout, cycle?by?cycle current limit, hiccup?mode overcurrent protection, hiccup?mode short?circuit protection. additional features include: programmable switching frequency, low quiescent current sleep mode and externally synchronizable switching frequency. features ? ultra low iq sleep mode ? adjustable output with 800 mv 2.0% reference voltage ? wide input of 3.1 to 44 v with undervoltage lockout (uvlo) ? programmable switching frequency ? internal soft?start (ss) ? fixed?frequency peak current mode control ? internal slope compensating artificial ramp ? internal high?side pmos gate driver ? regulated gate driver current source ? external frequency synchronization (sync) ? programmable cycle?by?cycle current limit (cl) ? hiccup overcurrent protection (ocp) ? output short circuit hiccup protection (scp) ? space?saving 8?pin soic package ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant www. onsemi.com marking diagram device package shipping ? ordering information soic?8 suffix d case 751 ncv8852dr2g soic?8 (pb?free) 2500/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 1 8 v8852xx alyw 1 8 v8852xx= specific device code xx = (blank), 01 a = assembly location l = wafer lot y = year w = work week = pb?free package rosc gdrv isns gnd vin fb comp en/sync pinout diagram 1 2 3 4 8 7 6 5 NCV885201D1R2G soic?8 (pb?free) 2500/tape & ree l
ncv8852 www. onsemi.com 2 figure 1. ncv8852 application diagram figure 2. ncv8852 simple block diagram rosc gdrv isns gnd vin vin vo fb comp en/sync 8 gdrv vin v ref drive logic fault logic csa isns 7 6 3 comp vea 5 gnd pwm scp ocp uvlo osc clamp 4 fb 2 en/sync ss cl 1 rosc en/sync + pin descriptions no pin symbol function 1 rosc use a resistor from ground to set the frequency. 2 en/sync enable and synchronization input. the falling edge synchronizes the internal oscillator. the part is disabled into sleep mode when this pin is brought low for longer than the enable time?out period. 3 comp output of the voltage error amplifier. an external compensator network from comp to gnd is used to sta- bilize the converter and tailor transient performance. 4 fb output voltage feedback. a resistor from the output voltage to fb with another resistor from fb to gnd creates a voltage divider for regulation and programming of the output voltage. 5 gnd ground reference. 6 gdrv gate driver output. connect to gate of the external p?channel mosfet. a series resistance can be added from gdrv to the gate to tailor emc performance. 7 isns current sense input. connect this pin to the source of the external p?channel mosfet, through a current? sense resistor to vin to sense the switching current for regulation and current limiting. 8 vin main power input for the ic.
ncv8852 www. onsemi.com 3 maximum ratings (voltages are with respect to gnd unless otherwise indicated.) rating value unit dc voltage (vin, isns, gdrv) ?0.3 to 44 v peak transient voltage (load dump on vin) 44 v dc voltage (en/sync) ?0.3 to 6.0 v dc voltage (comp, fb, rosc) ?0.3 to 3.6 v dc voltage stress (vin ? gdrv) ?0.7 to 12 v operating junction temperature range ?40 to 150 c storage temperature range ?65 to 150 c peak reflow soldering temperature: pb?free 60 to 150 seconds at 217 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. package attributes characteristic value esd capability human body model machine model charge device model 2.0 kv 200 v >1.0 kv moisture sensitivity level msl 1 260 c package thermal resistance junction?to?ambient, r ja 100 c/w
ncv8852 www. onsemi.com 4 electrical characteristics (v in = 3.4 v to 36 v, en = 5 v. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation) characteristic symbol conditions min typ max unit general quiescent current i q,sleep v in = 13.2 v, en = 0 v, sleep mode 2.5 6.0 a i q,off v in = 13.2 v, en = 5 v or toggled, v fb = 1 v, no switching 2.0 3.0 ma i q,on v in = 13.2 v, en = 5 v or toggled, v fb = 0 v, switching 3.0 5.0 ma undervoltage lockout v uvlo v in decreasing 2.9 3.1 3.3 v undervoltage lockout hysteresis v uvlo,hys 50 150 300 mv overvoltage lockout v ovlo 36.9 38 39.3 v oscillator switching frequency f sw 100 500 khz r osc voltage v rosc 1.0 v default switching f sw r osc = open r osc = 100 k r osc = 20 k r osc = 10 k 153 180 283 409 170 200 315 455 187 220 347 501 khz slope compensation m a 25.5 mv/ s minimum on time t onmin 90 110 140 ns max duty cycle ? switching d max,sw maximum duty cycle when switching 93 % max duty cycle d max 100 % soft?start time t ss 1.0 1.5 2.0 ms soft?start delay t ss,dlly 200 300 400 s en/sync low threshold v s,il 0.8 v high threshold v s,ih 2.0 v input current i sync 5.0 10 a sync frequency range f sync relative to nominal switching frequency 80 600 % sync delay t s,dly from sync falling edge to gdrv falling edge 50 100 ns sync duty cycle d sync 25 75 % disable delay time t en % of f sw 300 % voltage error amp dc gain a v 55 80 91 db gain?bandwidth product g bw 1.7 2.4 3.1 mhz fb bias current i vfb,bias 0.1 1.0 a charge currents i src,vea source, v fb = 0.9 v, v comp = 1.2 v 1.2 1.8 2.5 ma i snk,vea sink, v fb = 0.7 v, v comp = 1.2 v 0.5 0.8 1.0 reference voltage v ref 784 800 816 mv high saturation voltage v c,max 2.2 2.3 v low saturation voltage v c,min 0.001 0.3 v current sense amp common?mode range cmr 3.1 40 v differential mode range dmr 300 mv amplifier gain a csa 2.0 v/v
ncv8852 www. onsemi.com 5 electrical characteristics (v in = 3.4 v to 36 v, en = 5 v. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation) characteristic unit max typ min conditions symbol current sense amp input bias current i sns,bias ncv8852 ncv885201 30 70 50 120 a current limit / over current protection cycle?by?cycle current limit threshold v cl 85 100 115 mv cycle?by?cycle current limit response time t cl 200 nsec over current protection threshold v ocp % of v cl 125 150 175 % over current protection response time t ocp 200 ns gate drivers leading edge blanking time t on,min 100 ns gate driver pull up current i sink v in ? v gdrv = 4 v 200 300 ma gate driver pull down current i src v in ? v gdrv = 4 v 200 300 ma gate driver clamp voltage (v in ? v gdrv ) v drv 6.0 8.0 10 v power switch gate to source voltage v gs v in = 4 v 3.8 v short circuit protection startup blanking time t scp,dly from start of soft?start, % of soft?start time 105 300 % short?circuit threshold voltage v scp % of feedback voltage (v ref ) 65 70 75 % hiccup time t hcp,dly % of soft?start time 135 % sc response time t scp switcher running 60 200 ns thermal shutdown thermal shutdown threshold t sd t j rising 160 170 180 c thermal shutdown hysteresis t sd,hys t j shutdown ? t j startup 10 15 20 c thermal shutdown delay t tsd t j > thermal shutdown threshold to stop switching 200 ns
ncv8852 www. onsemi.com 6 typical characteristics curves t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 3. quiescent current (sleep) vs. junction temperature i q , quiescent current, sleep ( a) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 4. quiescent current vs. junction temperature i q , quiescent current ( a) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 switching no switching t j , junction temperature ( c) figure 5. reference voltage vs. junction temperature v ref , (v) ?50 ?25 0 25 50 150 125 100 75 0.79926 0.79924 0.79922 0.7992 0.79918 0.79916 0.79914 0.79912 0.7991 0.79908 0.79906 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 6. switching frequency (r osc = open) vs. junction temperature 174.5 174 173.5 173 172.5 172 171.5 171 170.5 170 169.5 f sw , (khz) t j , junction temperature ( c) figure 7. switching frequency (r osc = 10 k ) vs. junction temperature f sw , r osc = 10 k (v) ?50 ?25 0 25 50 150 125 100 75 466 464 462 460 458 456 454 452 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 8. short?circuit protection threshold vs. junction temperature 70.27 scp (% of v fb ) 70.26 70.25 70.24 70.23 70.22 70.21
ncv8852 www. onsemi.com 7 typical characteristics curves t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 9. minimum on time vs. junction temperature 111.2 minimum on time (ns) 111 110.8 110.6 110.4 110.2 110 109.8 109.6 109.4 109.2 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 10. gate drive current vs. junction temperature 230 gate drive current (ma) 225 220 215 210 205 sink source t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 11. cycle?by?cycle limit vs. junction temperature 111.2 cycle?by?cycle current limit (mv) 111 110.8 110.6 110.4 110.2 110 109.8 109.6 109.4 109.2 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 12. over current protection vs. junction temperature 150.2 over current protection (% v d ) 150 149.8 149.6 149.4 149.2 149 148.8 148.6 148.4 t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 13. uvlo threshold vs. junction temperature 3.4 uvlo (v) 3.35 3.3 3.25 3.2 3.15 3.1 3.05 3 falling rising t j , junction temperature ( c) ?50 ?25 0 25 50 150 125 100 75 figure 14. soft?start time vs. junction temperature 1.62 t ss (ms) 1.6 1.58 1.56 1.54 1.52 1.5 1.48
ncv8852 www. onsemi.com 8 theory of operation oscillator s r q + slope compensation ncv8852 vin isns current information voltage error vout gdrv compensation c o l csa vref pwm comparator gate drive - + figure 15. current mode control schematic comp fb ? + r sns r load vea current mode control the ncv8852 smps incorporates a current mode control scheme, in which the pwm ramp signal is derived from the power switch current. this ramp signal is compared to the output of the error amplifier to control the on?time of the power switch. the oscillator is used as a fixed?frequency clock to ensure a constant operational frequency. the resulting control scheme features several advantages over conventional voltage mode control. first, derived from the resistor in the power path, the signal responds immediately to line voltage changes. this eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. the second benefit comes from inherent pulse?by?pulse current limiting by merely clamping the peak switching current. finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. this allows for a simpler compensation. the ncv8852 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. a proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. overcurrent protection the ncv8852 features two current limit protections: peak current mode and overcurrent hiccup mode. when the current sense amplifier detects a voltage above the peak current limit between v in and isns after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. set the current limit with a resistor from v in to isns, with r = 0.100 / i limit . if the voltage across the current sense resistor exceeds the overcurrent threshold voltage the part enters overcurrent hiccup mode. the part will remain off for the hiccup time and then go through the power on reset procedure. short circuit hiccup protection when the output voltage falls below the short circuit trip voltage the part enters short circuit latch off. when a short is detected the ncv8852 disables the outputs and attempts to re?enable the outputs after the short circuit hiccup time. the part remains off for the hiccup time and then goes through the power on reset procedure. if the short has been removed then the output stage re?enables and operates normally; however, if the short is still present the cycle begins again. internal heat dissipation is kept to a minimum as current will only flow during the reset time of the protection circuitry. the hiccup mode is continuous until the short is removed.
ncv8852 www. onsemi.com 9 gate drive to turn on the p?channel mosfet, the gate driver turns on a current source to ground. a clamp ensures that the gate drive voltage does not exceed 10 v. when the clamp starts conducting the current source starts to turn off. to turn off the external mosfet, the gate driver turns on a current source to v in . 100% duty cycle operation each cycle, the oscillator allows either a maximum duty cycle up to 93% or 100% duty cycle operation. the oscillator does not allow duty cycles between 93% and 100%. every cycle, the oscillator determines whether an off?time is necessary. if so, the oscillator creates a duty cycle up to 93%. if an of f?time is not required, it can be skipped and 100% duty cycle is allowed for the cycle. below are a few examples of what this could look like on the switching node: figure 16. duty cycle timing a b d 1234 c 93% 93% 93% 100% 93% 100% 93% 100% 93% 100% 100% 100% 100% vbat vbat vbat vbat 93% 93% 93% a: continuous operation. each period has a duty cycle that is less than or equal to 93%. b: one off?time is skipped in period 3, while the minimum off?time is maintained in periods 1, 2, and 4. c: an off?time is skipped in period 1 and in period 3, while the minimum off?time is maintained in periods 2 and 4. d: low input voltage causes the ic to regulate at continuous 100% duty cycle (dropout). en/sync this pin has three modes. when a dc logic high (cmos/ttl compatible) voltage is applied to this pin the ncv8852 operates at the r osc programmed frequency. when a dc logic low voltage is applied to this pin the ncv8852 enters a low quiescent current sleep mode. when a square wave of at least 80% of the switching frequency is applied to this pin the switcher operates at the same frequency as the square wave. if the signal is slower than 80% of the switching frequency, it will be interpreted as enabling and disabling the part. the falling edge of the square wave corresponds to the start of the switching cycle. r osc the default setting is an open rosc pin, allowing the oscillator to run at 170 khz. adding a resistor to gnd increases the switching frequency. a resistor in series with a voltage source greater than 1.0 v will decrease the switching frequency. overvoltage lockout to protect the ic, if the voltage on the vin pin the exceeds v ovlo the ncv8852 will shutdown. when the voltage drops below this voltage the part will go through the normal soft start procedure. undervoltage lockout undervoltage lockout protection is engaged when the input voltage drops below the v uvlo signal. the part will remain off until the input voltage rises above the v uvlo value plus hysteresis. depending on the desired output voltage, it is possible to engage the short-circuit hiccup mode before undervoltage lockout occurs. soft?start to ensure moderate inrush current and reduce output overshoot, the ncv8852 features a soft start which periodically adds charge to a capacitor until the final reference voltage is achieved. charging does not depend on the switching frequency when using the rosc pin. when using an external sync signal, however, charging is based on the switching frequency. if, for example, the ncv8852 is synchronized to twice the free running (not synced) frequency, the soft start will be half as long.
ncv8852 www. onsemi.com 10 design methodology choosing external components for the ncv8852 encompasses the following design process: 1. define operational parameters 2. select switching frequency 3. select current sensor 4. select a mosfet 5. select a diode 6. select output inductor 7. select output capacitors 8. select compensator components (1) operating parameter definition first, select feedback resistors to choose the output voltage as follows: v out v ref r 1 r 2 r 2 where: v out : desired output voltage r 1 : upper feedback resistor (between vout and fb) [ ] r 2 : lower feedback resistor (between fb and gnd) [ ] for a 5.0 v output, set r 1 to 42.2 k and r 2 to 8.06 k . certain operating parameters must be defined before proceeding with the rest of the design. these are application dependent and include the following: v in : input voltage, range from minimum to maximum with a typical value [v] i out : output current, range from minimum to maximum with an initial startup value i cl : desired typical current limit a number of basic calculations must be performed up front to use in the design process, as follows: d min v out v in(max) d v out v in(typ) d max v out v in(min) where: d min : minimum duty cycle (ideal) [%] v in(max) : maximum input voltage [v] d: typical duty cycle (ideal) [%] v in(typ) : typical input voltage [v] d max : maximum duty cycle (ideal) [%] v in(min) : minimum input voltage [v] (2) switching frequency selection selecting the switching frequency is a trade?of f between component size and power losses. operation at higher switching frequencies allows the use of smaller inductor and capacitor values to achieve the same inductor current ripple and output voltage ripple. however, increasing the frequency increases the switching losses of the mosfets, leading to decreased ef ficiency, especially noticeable at light loads. typically, the switching frequency is selected to avoid interfering with signals of known frequencies. the graph in figure 17, below, shows the required resistance to program the frequency. from 200 khz to 500 khz, the following formula is accurate to within 3% of the expected value: r osc 2859 f sw 170 where: f sw : desired switching frequency [khz] r osc : resistor from rosc pin to gnd [k ] figure 17. frequency vs. rosc f sw (khz) 600 500 400 300 200 100 0 20 40 50 90 100 110 r osc (k ) 80 70 60 30 10 (3) current sensor selection current sensing for peak current mode control relies on the inductor current signal. this is translated into a voltage via a current sense resistor, which is then measured differentially by the current sense amplifier, generating a single?ended output to use as a signal. the easiest means of implementing this transresistance is through the use of a sense resistor in series with the source of the mosfet and vin. a sense resistor should be calculated as follows: r sns v cl i cl where: r sns : sense resistor [ ] v cl : current limit threshold voltage [v] i cl : desired cycle?by?cycle current limit [a]
ncv8852 www. onsemi.com 11 (4) mosfet selection the ncv8852 has been designed to work with a p?channel mosfet in a non?synchronous buck configuration. the mosfet needs to be capable of handling the maximum allowable current in the system, i cl . keep in mind that, depending on your minimum v in signal, it is possible to achieve 100% duty cycle. the power dissipated through the mosfet during conduction is as follows: p mos,on i cl 2 d max r ds,on where: p mos,on : power through mosfet [ w ] i cl : cycle?by?cycle current limit [a] r ds,on : on?resistance of the mosfet [ ] to calculate the switching losses through the mosfet, use the following equation: p mos,sw 1 2 v in i out t on t off f sw t on t off q gate i drv where: p mos, sw : mosfet switching losses [w] t on : time to turn on the mosfet [s] t off : time to turn off the mosfet [s] q gate : gate charge [c] i drv : gate drive current [a] (5) diode selection the diode must be chosen according to its maximum current and voltage ratings, and to thermal considerations. the maximum reverse voltage the diode sees is the maximum input voltage (with some margin in case of ringing on the switch node). the maximum forward current is the peak current limit of the ncv8852, or 150% of i cl . (6) output inductor selection both mechanical and electrical considerations influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in the power supply, a minimum inductor value is particularly important in space? constrained applications. from an electrical perspective, an inductor is chosen for a set amount of current ripple and to assure adequate transient response. the output inductor controls the current ripple that occurs over a switching period. a high current ripple will result in excessive power loss and ripple current requirements. a low current ripple will result in a poor control signal and a slow current slew rate in the event of a load transient. a good starting point for peak?to?peak ripple is around 10% of the inductor current.to choose the inductor value based on the peak?to?peak ripple current, use the following equation: i l v out (1 d min ) l f sw where: i l : peak?to?peak output current ripple [ap?p] from this equation it is clear that the ripple current increases as l decreases, emphasizing the trade?off between dynamic response and ripple current. the peak and valley values of the triangular current waveform are as follows: i l(pk) i out i l 2 i l(vly) i out i l 2 where: i l(pk) : peak (maximum) value of ripple current [a] i l(vly) : valley (minimum) value of ripple current [a] saturation current is specified by inductor manufacturers as the current at which the inductance value has dropped from the nominal value, typically 10%. for stable operation, the output inductor must be chosen so that the inductance is close to the nominal value even at the peak output current, i l(pk) , it is recommended to choose an inductor with saturation current sufficiently higher than the peak output current, such that the inductance is very close to the nominal value at the peak output current. this allows for a safety factor and allows for more optimized compensation. inductor efficiency is another consideration when selecting an output inductor. inductor losses include dc and ac winding losses, which are very low due to high core resistance, and magnetic hysteresis losses, which increase with peak?to?peak ripple current. core losses also increase as switching frequency increases. ac winding losses are based on the ac resistance of the winding and the rms ripple current through the inductor, which is much lower than the dc current. the ac winding losses are due to skin and proximity effects and are typically much less than dc losses, but increase with frequency. dc winding losses account for a large percentage of output inductor losses and are the dominant factor at switching frequencies at or below 500 khz. the dc winding losses in the inductor can be calculated with the following equation: p l(dc) i out 2 r dc where: p l(dc) : dc winding losses in the output inductor r dc : dc resistance of the output inductor (dcr)
ncv8852 www. onsemi.com 12 (7) output capacitor selection the output capacitor is a basic component for the fast response of a power supply. in fact, for the first few microseconds of a load transient, they supply the current to the load. the controller recognizes the load transient and proceeds to increase the duty cycle to its maximum. neglecting the effect of the esl, the output voltage has a first drop due to esr of the bulk capacitor(s). v out(esr) i out esr a lower esr produces a lower v during load transient. in addition, a lower esr produces a lower output voltage ripple. in the case of stepping into a short, the inductor current approaches zero with the worst case initial current at the current limit and the initial voltage at the output voltage set point, calculating the voltage overshoot as follows: v os l i cl 2 c v out 2 v out accordingly, a minimum amount of capacitance can be chosen for maximum allowed output voltage overshoot: c min l i cl 2 v out v os(max) 2 v out 2 where: c min : minimum amount of capacitance to minimize voltage overshoot to v os(max) [f] v os(max) : maximum allowed voltage overshoot during a short [v] (8) select compensator components the current mode control method employed by the ncv8852 allows the use of a simple, type ii compensation to optimize the dynamic response according to system requirements. using a simulation tool such as compcalc can assist in the selection of these components.
ncv8852 www. onsemi.com 13 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv8852/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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